Design of 2.5V, 900MHz phase-locked loop (PLL) using 0.25μm TSMC CMOS technology

Author

Seng, Lee Ping ; Zulkifli, Tun Zainal Azni ; Noh, Norlaili Mohd ; Saibon, Basir

Author_Institution

Sch. of Electr. & Electron. Eng., Univ. Sains Malaysia, Seberang Perai Selatan, Malaysia

fYear

2004

Abstract

In this paper, a 2.5V, operating at 900MHz phase-locked loop implemented in 0.25μm TSMC CMOS process technology is presented. A high speed PFD is implemented using true-single-phase clock (TSPC) technique which manages to operate up to 1.1 GHz. VCO using ring oscillator with dual-delay path scheme is implemented to achieve 900MHz operation frequency with wider tuning range. The PLL manage to lock within 100ns. The PLL implementation only needs 67 transistors and consumes 23.81mW.

Keywords

CMOS analogue integrated circuits; UHF integrated circuits; UHF oscillators; clocks; integrated circuit design; phase detectors; phase locked loops; voltage-controlled oscillators; 0.25 micron; 100 ns; 2.5 V; 23.81 mW; 900 MHz; TSMC CMOS technology; dual-delay path scheme; high speed PFD; phase-locked loop; ring oscillators; true-single-phase clock technique; voltage controlled oscillators; CMOS process; CMOS technology; Charge pumps; Clocks; Filters; Phase detection; Phase frequency detector; Phase locked loops; Voltage control; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

Semiconductor Electronics, 2004. ICSE 2004. IEEE International Conference on

Print_ISBN

0-7803-8658-2

Type

conf

DOI

10.1109/SMELEC.2004.1620920

Filename

1620920