A low-power 1.92MHz CT ΔΣ modulator with 5-bit successive approximation quantizer

CT Delta-Sigma modulators provide a solution for low-power analog to digital conversion with built in anti-aliasing but they are sensitive to clock jitter. One way of mitigating the jitter problem is to use a multi-bit quantizer with increased number of bits. The limiting factors are quantizer delay and exponential growth of power and complexity. This paper reports the use of a 5-bit successive approximation ADC in a wide-band CT delta-sigma. The ADC structure allows easy integration of the delay compensation mechanism with minimum hardware and power. The design is implemented in a 130 nm CMOS technology and measurement results show a 62 dB dynamic range and 3.1 mW power consumption from a 1.2 V supply.