Title :
The role of partitioning in Time Warp simulation
Author :
Chi, Bob Y. ; Jiang, Hong
Author_Institution :
Lucent Technol., AT&T Bell Labs., Allentown, PA, USA
Abstract :
This paper examines one of the major issues associated with Time Warp simulation-the impact of partitioning on the Time Warp performance. The experimental work described, which uses a combination of a network of transputers and a multiprocessor emulator, focuses on the impact of partitioning on the simulation performance. Various results from the Time Warp simulation of a number of test circuits are obtained and presented. The simulation execution times using different partitioning strategies are compared and relevant analysis is made. A number of models are proposed and derived. The experimental results show that a good partitioning strategy, such as the bh method proposed in this work, is critical in improving the Time Warp simulation performance in an environment where the simulation problems contain loop structures and the off-processor communication cost per message is high. In addition, the results obtained from various experiments are consistent with the models proposed in this work
Keywords :
graph theory; multiprocessing systems; time warp simulation; transputer systems; bh method; discrete event simulation; loop structures; multiprocessor emulator; off-processor communication cost; parallel processing; partitioning; simulation execution times; test circuits; time warp simulation; transputer networks; Analytical models; Circuit simulation; Circuit testing; Clocks; Computer science; Cost function; Discrete event simulation; Distributed processing; Time warp simulation; Very large scale integration;
Conference_Titel :
Aerospace and Electronics Conference, 1997. NAECON 1997., Proceedings of the IEEE 1997 National
Conference_Location :
Dayton, OH
Print_ISBN :
0-7803-3725-5
DOI :
10.1109/NAECON.1997.618083