DocumentCode :
1704514
Title :
Lateral power MOSFET low-doped drain (LDD) misalignment test structure
Author :
Vitomirov, I.M. ; Seabridge, S.N. ; Raisanen, A.D. ; Tellier, T.
Author_Institution :
Xerox Corp., Webster, NY, USA
fYear :
1997
Firstpage :
31
Lastpage :
34
Abstract :
We have designed and evaluated an electrical test structure capable of detecting sub-micron shifts in the alignment of the Low-Doped Drain (LDD) region relative to the gate of a lateral power MOSFET. The test structure consists of four identical high-voltage transistors geometrically rotated in 90° increments relative to each other. Under suitable transistor biasing conditions, a shift in the position of the mask defining the edge of the LDD region is shown to produce a linear response in the IDS of the affected test transistors. The dependence of the transistor current on the LDD region length is then used to electrically monitor this critical mask alignment
Keywords :
MOS integrated circuits; field effect transistor switches; masks; power MOSFET; power integrated circuits; semiconductor device testing; electrical test structure; high-voltage transistors; lateral power MOSFET; linear response; low-doped drain region; mask misalignment; sub-micron shifts; transistor biasing conditions; transistor current; Electric variables measurement; Electrical resistance measurement; Ink; MOSFET circuits; Power MOSFET; Power integrated circuits; Power transistors; Printing; Testing; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Microelectronic Test Structures, 1997. ICMTS 1997. Proceedings. IEEE International Conference on
Conference_Location :
Monterey, CA
Print_ISBN :
0-7803-3243-1
Type :
conf
DOI :
10.1109/ICMTS.1997.589321
Filename :
589321
Link To Document :
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