Lateral power MOSFET low-doped drain (LDD) misalignment test structure

We have designed and evaluated an electrical test structure capable of detecting sub-micron shifts in the alignment of the Low-Doped Drain (LDD) region relative to the gate of a lateral power MOSFET. The test structure consists of four identical high-voltage transistors geometrically rotated in 90° increments relative to each other. Under suitable transistor biasing conditions, a shift in the position of the mask defining the edge of the LDD region is shown to produce a linear response in the I_DS of the affected test transistors. The dependence of the transistor current on the LDD region length is then used to electrically monitor this critical mask alignment