A minimum decap allocation technique based on simultaneous switching for nanoscale SoC

In this paper, we propose a novel decoupling capacitance (decap) optimization technique based on simultaneous cell switching activity at the pre-layout stage. White space in the form of cell padding for the required quantity of decap is added to cells which simultaneously switch during the peak noise period, which is quickly estimated using initial timing information and the current waveforms for each cell instance, without the need to reference the power grid. The method is applied to an actual 45nm LSI and results show a 35% decap area reduction or 21.9% peak noise reduction compared with conventional decap insertion flows. The technique can improve the reliability of SoC with a runtime overhead of only 1% at the P&R stage in existing nanoscale SoC EDA design flows.