Worst-case clock delay simulation under PG variation using gradient projection method

This paper describes a novel method for worst case clock delay verification under power ground variation. Based on our simulation tool using topology reduction and hierarchical relaxation method, a generalization of the gradient projection method, which tries to find a next feasible iteration point using the projection of the sensitivity at the current iteration point, is used to find a worst case delay of the clock network under power ground voltage variation. Our experiment demonstrates that the method always converges at several iteration steps and thus it is both accurate and computationally efficient.