Via assignment algorithm for hierarchical 3D placement

Three-dimensional (3D) packaging technologies are now emerging to alleviate the interconnect delay problem, increase transistor packing density and reduce chip area. In 3D integration, vertical vias are utilized to realize interconnections between stacked layers. Route planning for these vertical wires by via assignment are of great importance for wirelength reduction, congestion alleviation and thermal optimization. Different via assignment algorithms are proposed for wirelength optimization. These methods are integrated in a hierarchical 3D design flow for mixed-mode placement (MMP). The experimental results show that total wirelength can be reduced by 8% with sacrifice on the runtime. Our algorithms are proved to be very effective and efficient.