A hot-spot identification method in VLSI BBL placement

The trends in microelectronic design go toward increased component integrated density and higher power consumed. The thermal management has been a more prominent role in recent year. Therefore, an accurate thermal model was needed to develop a new placement algorithm designed to consider both minimizing chip area and making the chip thermal distribution even. The simulated annealing vas employed in our algorithm. The experimental results show that the thermal distribution was even and the temperature of the "hot spots" decreased greatly in the chip.