Title :
A sub-0.75°RMS-phase-error differentially-tuned fractional-N synthesizer with on-chip LDO regulator and analog-enhanced AFC technique
Author :
Lu, Lei ; Meng, Lingbu ; Zou, Liang ; Min, Hao ; Tang, Zhangwen
Author_Institution :
ASIC & Syst. State Key Lab., Fudan Univ., Shanghai, China
Abstract :
This paper presents a low-phase-error wideband fractional-N frequency synthesizer. Differential tuning is described and a level shift circuit is proposed to obtain symmetrical tuning range. On-chip LDO regulator is designed to improve the power supply rejection for VCO. A voltage monitor is used to enhance the digital AFC technique to overcome the temperature variation. The synthesizer was implemented in a 0.18-mum CMOS process with a 16-mA supply current and a 1.47-mm2 die area. The measured in-band phase noise is less than -97 dBc/Hz at a 10-kHz frequency offset and the integrated phase error is less than 0.75degRMS. The measured reference spur is less than -71 dBc and the locking time is smaller than 20 mus.
Keywords :
CMOS integrated circuits; UHF circuits; calibration; circuit tuning; delta-sigma modulation; frequency synthesizers; voltage-controlled oscillators; CMOS process; VCO; analog-enhanced AFC technique; automatic frequency calibration; current 16 mA; delta-sigma synthesizer; differential tuning; differentially-tuned fractional-N synthesizer; digital AFC technique; frequency 10 kHz; in-band phase noise; level shift circuit; low-dropout regulator; on-chip LDO regulator; phase-error synthesizer; power supply rejection; size 0.18 mum; voltage monitor; wideband synthesizer; Automatic frequency control; Circuit optimization; Frequency synthesizers; Monitoring; Power supplies; Regulators; Temperature; Voltage; Voltage-controlled oscillators; Wideband;
Conference_Titel :
Custom Integrated Circuits Conference, 2009. CICC '09. IEEE
Conference_Location :
San Jose, CA
Print_ISBN :
978-1-4244-4071-9
Electronic_ISBN :
978-1-4244-4073-3
DOI :
10.1109/CICC.2009.5280924
