Implementation of Data Acquisition and Processing IP core for Digital Protective Relay

This paper introduces a multi-channels data synchronous acquisition and processing IP (intellectual property) core for digital protective relay. It integrates data acquisition and processing in one FPGA, resolving problem of asynchrony between data acquisition and data processing as well as setting of the number of sampling channels and sampling points per period. In contrast to the traditional acquisition system, it has characteristic of high speed, flexibility and low cost. This IP core was verified in FPGA (field programmable gate array) based hardware platform. The result of experiment indicates that this IP core is correct and can be used into SOC (system on chip) application as a single module.