High density, low cost packaging and interconnect technology

Author

Garrou, Philip

Author_Institution

MCNC, Research Triangle Park, NC, USA

fYear

1998

Firstpage

10

Lastpage

17

Abstract

The increase of I/O on chip is driving chip, package and board interconnect schemes to alternative technologies. Area array flip chips and BGAs are beginning to replace peripheral pad limited chips and tight pitch leads on PQFPs. The PWB industry is looking at technologies which form “microvias” to handle the interconnection of these high density chip/package formats. New technologies such as large area processing (LAP) and seamless high off chip connectivity (SHOCC) are being developed to meet these needs

Keywords

ball grid arrays; flip-chip devices; integrated circuit interconnections; integrated circuit packaging; printed circuits; technological forecasting; BGAs; PQFP lead pitch; PWB industry; SHOCC; area array flip chips; board interconnect schemes; chip interconnect schemes; high density chip/package format interconnection; high density packaging; interconnect technology; large area processing; low cost packaging; microvias; on chip I/O; package interconnect schemes; peripheral pad limited chips; seamless high off chip connectivity; Application specific integrated circuits; Bonding; Capacitive sensors; Chemical technology; Costs; Driver circuits; Electronics industry; Flip chip; Logic devices; Packaging;

fLanguage

English

Publisher

ieee

Conference_Titel

IEMT/IMC Symposium, 2nd 1998

Conference_Location

Tokyo

Print_ISBN

0-7803-5090-1

Type

conf

DOI

10.1109/IEMTIM.1998.704499

Filename

704499