Title :
IDDQ test generation for BF fault in combinational circuit based on genetic algorithms
Author :
Xie, Hua ; Wang, Houjun
Author_Institution :
Sch. of Autom. Eng., Univ. of Electron. Sci. & Technol. of China, Chengdu, China
Abstract :
This paper presents an improved genetic algorithm to generate compact test sets for IDDQ testing for bridging faults in combinational circuits. Through local optimizing, choosing BF faults, genetic algorithms, the faults test sets are generated gradually and the faults are tested and located fast through our algorithm. The simulation results on an ISCAS´85 circuit show the validity of the algorithm for generation of fault test set.
Keywords :
combinational circuits; fault location; genetic algorithms; integrated circuit testing; logic testing; BF fault; IDDQ test generation; ISCAS85 circuit; bridging faults; combinational circuit; fault testing; genetic algorithms; Circuit faults; Circuit simulation; Circuit testing; Combinational circuits; Dictionaries; Electrical fault detection; Electronic equipment testing; Fault diagnosis; Genetic algorithms; Semiconductor device modeling;
Conference_Titel :
Communications, Circuits and Systems, 2005. Proceedings. 2005 International Conference on
Print_ISBN :
0-7803-9015-6
DOI :
10.1109/ICCCAS.2005.1495358
