A shared-bus control mechanism and a cache coherence protocol for a high-performance on-chip multiprocessor

A new cache coherence solution is proposed for an over 500 MHz on-chip multiprocessor using advanced VLSI technology. In order to reduce shared-bus transaction time, the central coherence unit (CCU) is introduced. The CCU controls all shared-bus transactions, monitoring all cache rays every clock cycle, and executes a bus transaction in four clock cycles while a conventional bus mechanism requires eight clock cycles. A new cache coherence protocol (CRAC) is also introduced in order to reduce external memory access. The CRAC protocol makes it possible to load a desired data from any cache having a copy, and to transfer write-back responsibility to another cache having a copy. An implementation of CCU and CRAC is presented and evaluated using a cycle-based multiprocessor simulator. Simulation results show that introduction of CCU and CRAC is effective to reduce shared-bus traffic and total execution time. Furthermore, proposed multiprocessor model with CCU and CRAC is proved to be more scalable than a conventional multiprocessor model