• DocumentCode
    1705655
  • Title

    Distance-adaptive update protocols for scalable shared-memory multiprocessors

  • Author

    Raynaud, Alain ; Zhang, Zheng ; Torrellas, Josep

  • Author_Institution
    Center for Supercomput. Res. & Dev., Illinois Univ., Urbana, IL, USA
  • fYear
    1996
  • Firstpage
    323
  • Lastpage
    334
  • Abstract
    While update protocols generally induce lower miss rates than invalidate protocols, they tend to generate much traffic. This is one of the reasons why they are considered less cost-effectively scalable than invalidate protocols and, as a result, are avoided in most existing designs of scalable shared-memory multiprocessors. However, given the increasing relative cost of cache misses, update protocols are becoming more worthy of exploration. In this paper, we present a model of sharing that is key to investigating the performance of optimized update protocols: the update distance model. The model gives insight into the update patterns that optimized protocols need to handle. Using this model, we design a new family of protocols that we call distance-adaptive protocols. In these schemes, the directory records the update patterns observed and then uses them to selectively send updates and invalidations to processors. As a result, traffic and miss rates are kept low. We present an implementation of these protocols based on a dynamic pointer scheme. A performance comparison between one of these protocols and efficient invalidate and delayed competitive-update protocols over five applications shows that the new protocol decreases the execution time by an average of 15% and 10% respectively
  • Keywords
    performance evaluation; protocols; shared memory systems; directory; distance-adaptive update protocols; dynamic pointer scheme; performance; scalable shared-memory multiprocessors; Access protocols; Contracts; Costs; Delay effects; Multithreading; NASA; Prefetching; Research and development; Telecommunication traffic; Traffic control;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    High-Performance Computer Architecture, 1996. Proceedings., Second International Symposium on
  • Conference_Location
    San Jose, CA
  • Print_ISBN
    0-8186-7237-4
  • Type

    conf

  • DOI
    10.1109/HPCA.1996.501197
  • Filename
    501197