11-bit floating-point pipelined analog to digital converter in 0.18μm CMOS

In many integrated sensor systems applications where signals of high dynamic range have to be sampled with a good precision, large dynamic range nonuniform analog to digital converters (ADC) are often a preferred solution. Using the floating-point compression technique increases the dynamic range of the ADC and reduces the number of output bits, thus helping to reduce the data transmission bandwidth and storage memory. The pipelined structure of the ADC reduces the number of components and therefore, the power consumption to a low 50 mW level, while keeping the high sampling rate equal to the clock speed of up to 10 Msample/sec. The peak signal to noise ratio of the conversion is 48 dB. This project is done in CMOS 0.18 μm technology.