Time-differential sense amplifier for sub-80mV bitline voltage embedded STT-MRAM in 40nm CMOS

Author

Jefremow, M. ; Kern, T. ; Allers, W. ; Peters, C. ; Otterstedt, J. ; Bahlous, O. ; Hofmann, Klaus ; Allinger, R. ; Kassenetter, S. ; Schmitt-Landsiedel, Doris

Author_Institution

Infineon Technol., Neubiberg, Germany

fYear

2013

Firstpage

216

Lastpage

217

Abstract

Spin-torque-transfer (STT) MRAM is a promising candidate for embedded non-volatile memory in next generation microcontrollers, because of superior endurance, low process costs and logic supply voltage operation. Two major drawbacks of STT-MRAM technology are the small read window because of the low tunnel magnetic resistance (TMR) ratio, and the low read current due to read disturb, which is proportional to the bitline (BL) voltage [1].

Keywords

CMOS digital integrated circuits; MRAM devices; differential amplifiers; CMOS; TMR ratio; embedded nonvolatile memory; logic supply voltage operation; low process costs; next generation microcontrollers; read current; read disturb; read window; size 40 nm; spin-torque-transfer; sub-bitline voltage embedded STT-MRAM; time-differential sense amplifier; tunnel magnetic resistance ratio; voltage 80 mV; Accuracy; Computer architecture; Electric potential; Logic gates; Sensors; Voltage control; Voltage measurement;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2013 IEEE International

Conference_Location

San Francisco, CA

ISSN

0193-6530

Print_ISBN

978-1-4673-4515-6

Type

conf

DOI

10.1109/ISSCC.2013.6487706

Filename

6487706