Author :
Naso, G. ; Botticchio, L. ; Castelli, Marco ; Cerafogli, C. ; Cichocki, M. ; Conenna, P. ; d´Alessandro, Antonio ; Santis, L.D. ; Cicco, D.D. ; Francesco, W.D. ; Gallese, M.L. ; Gallo, G. ; Incarnati, M. ; Lattaro, C. ; Macerola, A. ; Marotta, G. ; Moschi
Abstract :
The authors develop a 128Gb 3b/cell NAND Flash memory based on 20nm fully planar cell process technology. The planar cell allows the memory cell to be scaled in both the wordline (WL) and bitline (BL) directions, resulting in a small 3b/cell memory device. The sensing scheme is based on a ramping technique that allows the detection of hard and soft states in a single operation.
Keywords :
NAND circuits; flash memories; integrated circuit design; 3b-cell memory device; BL directions; NAND flash design; WL directions; bitline directions; fully planar cell process technology; hard states; ramping technique; sensing scheme; size 20 nm; soft states; wordline directions; Flash memories; Interference; Logic gates; Metals; Nonvolatile memory; Random access memory; Sensors;
