DocumentCode
1706227
Title
A 128Gb 3b/cell NAND flash design using 20nm planar-cell technology
Author
Naso, G. ; Botticchio, L. ; Castelli, Marco ; Cerafogli, C. ; Cichocki, M. ; Conenna, P. ; d´Alessandro, Antonio ; Santis, L.D. ; Cicco, D.D. ; Francesco, W.D. ; Gallese, M.L. ; Gallo, G. ; Incarnati, M. ; Lattaro, C. ; Macerola, A. ; Marotta, G. ; Moschi
Author_Institution
Micron, Avezzano, Italy
fYear
2013
Firstpage
218
Lastpage
219
Abstract
The authors develop a 128Gb 3b/cell NAND Flash memory based on 20nm fully planar cell process technology. The planar cell allows the memory cell to be scaled in both the wordline (WL) and bitline (BL) directions, resulting in a small 3b/cell memory device. The sensing scheme is based on a ramping technique that allows the detection of hard and soft states in a single operation.
Keywords
NAND circuits; flash memories; integrated circuit design; 3b-cell memory device; BL directions; NAND flash design; WL directions; bitline directions; fully planar cell process technology; hard states; ramping technique; sensing scheme; size 20 nm; soft states; wordline directions; Flash memories; Interference; Logic gates; Metals; Nonvolatile memory; Random access memory; Sensors;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2013 IEEE International
Conference_Location
San Francisco, CA
ISSN
0193-6530
Print_ISBN
978-1-4673-4515-6
Type
conf
DOI
10.1109/ISSCC.2013.6487707
Filename
6487707
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