A transaction-level framework for design-space exploration of hardware-enhanced operating systems

The increasing number of processing elements on embedded many-cores gives novel challenges for the chip design. Dedicated hardware has become an important feature to support the applied operating system and to improve the overall system efficiency. Since evaluation of novel architectures requires time expensive simulations or prototyping, transaction-level analysis gives an appropriate tool for early design stage evaluation. This work proposes a transaction-level framework for simulating hardware-enhanced many-core operating systems. The framework allows the design space exploration of the hardware and software architecture and uses a trace-based task description language including a customized interface for system calls.