Title :
Unified solid-state-storage architecture with NAND flash memory and ReRAM that tolerates 32× higher BER for big-data applications
Author :
Tanakamaru, Shuhei ; Doi, M. ; Takeuchi, Ken
Author_Institution :
Chuo Univ., Tokyo, Japan
Abstract :
Unified solid-state storage (USSS) provides high error tolerance with four techniques: reverse-mirroring (RM), error-reduction synthesis (ERS), page-RAID, and error-masking (EM). The acceptable raw bit-error rate (ABER) of NAND flash memory is enhanced by 32×, or endurance or data-retention time effectively extends by 4.2 or 34×, respectively. ABER is defined to realize BER after ECC below 10-15.
Keywords :
NAND circuits; error statistics; flash memories; ABER; ECC; EM; ERS; NAND flash memory; RM; ReRAM; USSS; acceptable raw bit-error rate; big-data applications; data-retention time; endurance time; error tolerance; error-masking; error-reduction synthesis; page-RAID; reverse-mirroring; unified solid-state-storage architecture; Bit error rate; Buffer storage; Error correction codes; Flash memories; Mirrors; Redundancy; Servers;
Conference_Titel :
Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2013 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4673-4515-6
DOI :
10.1109/ISSCC.2013.6487711
