Limits of gate-level power estimation considering real delay effects and glitches

Gate-level power estimation based on foundry-supplied standard cell libraries is a common analysis step during digital design. Surprisingly little is known about the accuracy of this approach and the suitability for different circuit types. At the same time, commercial tools implementing this approach are employed broadly and often regarded as the reference when comparing estimation methodologies on higher levels of abstraction. This work evaluates the suitability and accuracy of gate level power estimators for combinatorial circuits of different logic depths in order to test the ability of handling real gate delay effects. While the basic methodology leads to estimation errors of up to 32 % for the tested circuits, by various improvements in the work flow the accuracy can be improved at the cost of longer runtimes. Apart from recommendations on improving accuracy this work identifies shortcomings in the established approach and highlights circuit characteristics that tend to influence estimation accuracy.