Improve clock gating through power-optimal enable function selection

Clock gating technology can reduce the consumption of clock signals´ switching power of flip-flops. The clock gate enable functions can be identified by Boolean analysis of the logic inputs for all flip flops. However, the enable functions of clock gate can be further simplified, and the average number of flip flops driven by enable functions can be improved. In this way, the circuit area can be reduced; therefore, the clock gating can be improved and power saving can be achieved. This paper presents a technique for improving clock gating by optimizing the enable functions. The problem of improving clock gating is formulated as finding the optimal set of enable functions in the shared logic cone that leads to best power reduction on flip flops. First, enable functions are identified by random simulation and SAT. Then the optimal set of enable functions is found with partition method. This paper demonstrates the effectiveness of the approach through testing on MCNC benchmarks and industrial circuits. The experimental results show that the algorithm will get as much power saving as 3 times of that of the original clock gating circuits, and all benchmarks can run in tens of seconds.