DocumentCode
1706562
Title
A fast untestability proof for SAT-based ATPG
Author
Tille, Daniel ; Drechsler, Rolf
Author_Institution
Inst. of Comput. Sci., Univ. of Bremen, Bremen
fYear
2009
Firstpage
38
Lastpage
43
Abstract
Automatic Test Pattern Generation (ATPG) based on Boolean satisfiability (SAT) has been shown to be a beneficial complement to traditional ATPG techniques. SAT solvers work on instances given in Conjunctive Normal Form (CNF). The required transformation of the ATPG problem into CNF is one main part of SAT-based ATPG and needs a significant portion of the overall run time. Solving the SAT instance is the other main part. Here, the time needed is often negligible - especially for easy-to-classify untestable faults. This paper presents a preprocessing technique that speeds up the classification of untestable faults by accelerating the SAT instance generation. This increases the robustness of the entire ATPG process. The efficiency of the proposed method is shown by experiments on large industrial designs.
Keywords
circuit testing; network synthesis; Boolean satisfiability; SAT-based ATPG; automatic test pattern generation; industrial designs; untestable faults; Acceleration; Automatic test pattern generation; Buildings; Circuit faults; Circuit synthesis; Circuit testing; Computer science; Electronic design automation and methodology; Robustness; Test pattern generators;
fLanguage
English
Publisher
ieee
Conference_Titel
Design and Diagnostics of Electronic Circuits & Systems, 2009. DDECS '09. 12th International Symposium on
Conference_Location
Liberec
Print_ISBN
978-1-4244-3341-4
Electronic_ISBN
978-1-4244-3340-7
Type
conf
DOI
10.1109/DDECS.2009.5012096
Filename
5012096
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