An all-digital PLL using random modulation for SSC generation in 65nm CMOS

Author

Da Dalt, Nicola ; Pridnig, P. ; Grollitsch, W.

Author_Institution

Infineon Technol., Villach, Austria

fYear

2013

Firstpage

252

Lastpage

253

Abstract

This paper introduces a digital PLL which uses high-frequency random modulation (RM), as opposed to low-frequency periodic modulation, to generate a spread spectrum clock (SSC). The implementation is straightforward and reduces accumulated jitter substantially (by a factor of 8 in our implementation) with no penalty to EMI reduction or to period jitter. As a key advantage, the proposed design allows one to reduce the depth of FIFOs needed for high-data-rate peripherals or to remove it completely in case of low-data-rate interfaces.

Keywords

CMOS integrated circuits; digital phase locked loops; jitter; modulation; radiofrequency integrated circuits; radiofrequency interference; spread spectrum communication; EMI reduction; FIFO; SSC generation; accumulated jitter; all-digital PLL; high-data-rate peripherals; high-frequency RM; high-frequency random modulation; low-data-rate interfaces; low-frequency periodic modulation; period jitter; size 65 nm; spread spectrum clock; Clocks; Electromagnetic interference; Frequency modulation; Jitter; Phase locked loops; Temperature measurement;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2013 IEEE International

Conference_Location

San Francisco, CA

ISSN

0193-6530

Print_ISBN

978-1-4673-4515-6

Type

conf

DOI

10.1109/ISSCC.2013.6487722

Filename

6487722