• DocumentCode
    1706636
  • Title

    A 2.5GHz 2.2mW/25µW on/off-state power 2psrms-long-term-jitter digital clock multiplier with 3-reference-cycles power-on time

  • Author

    Anand, Tejasvi ; Talegaonkar, Mrunmay ; Elshazly, Amr ; Young, B. ; Hanumolu, Pavan Kumar

  • Author_Institution
    Oregon State Univ., Corvallis, OR, USA
  • fYear
    2013
  • Firstpage
    256
  • Lastpage
    257
  • Abstract
    Modern mobile platforms utilize power cycling to lower power dissipation and increase battery life. By turning off the circuits that are not in use, power cycling provides a viable means to make power dissipation proportional to workload, hence achieving energy proportional operation. The effectiveness of this approach is governed by the turn on/off times, off-state power dissipation, and energy overhead due to power-cycling. Ideally, the circuits must turn on/off in zero time, consume no off-state power, and incur minimal energy overhead during on-to-off and off-to-on transitions. Conventional clock multipliers implemented using phase-locked loops (PLLs) present the biggest bottleneck in achieving these performance goals due to their long locking times. Even if the PLL is frequency locked, the slow phase acquisition process limits the power-on time [1-2]. Techniques such as dynamic phase-error compensation [3], edge-missing compensation [4], and hybrid PLLs [5] improve the phase acquisition time to at best few hundred reference cycles. However, such improvements are inadequate to make best use of power-cycling. Multiplying injection-locked oscillators (MILO) are shown to lock faster than PLLs, but suffer from conflicting requirements on injection strength to simultaneously achieve low jitter and fast locking. Increasing the injection strength extends lock range and reduces locking time, but severely degrades the deterministic jitter performance [6]. In view of these drawbacks, we propose a highly digital clock multiplier that seeks to achieve low jitter, fast locking, and near-zero off-state power. By using a highly scalable digital architecture with accurate frequency presetting and instantaneous phase acquisition, the prototype 8×/16× clock multiplier achieves 10ns (3 reference cycles) power-on time, 2psrms long-term absolute jitter, less than 25μW off-state power, 12pJ energy overhead for on/off transition, and 2.2mW on-state - ower at 2.5GHz output frequency.
  • Keywords
    battery management systems; clocks; error compensation; injection locked oscillators; jitter; multiplying circuits; phase locked loops; PLL; battery life; clock multipliers; deterministic jitter performance; digital architecture; digital clock multiplier; dynamic phase error compensation; edge missing compensation; energy overhead; energy proportional operation; frequency 2.5 GHz; instantaneous phase acquisition; mobile platforms; multiplying injection locked oscillators; near zero offstate power; offstate power dissipation; phase locked loops; power 2.2 mW; power 25 muW; power cycling; reference cycles; Capacitors; Clocks; Jitter; Oscillators; Phase locked loops; Solid state circuits; Time-frequency analysis;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2013 IEEE International
  • Conference_Location
    San Francisco, CA
  • ISSN
    0193-6530
  • Print_ISBN
    978-1-4673-4515-6
  • Type

    conf

  • DOI
    10.1109/ISSCC.2013.6487724
  • Filename
    6487724