• DocumentCode
    170681
  • Title

    A compiler framework for automatically mapping data parallel programs to heterogeneous MPSoCs

  • Author

    Chandramohan, Kiran ; O´Boyle, Michael F. P.

  • Author_Institution
    Sch. of Inf., Univ. of Edinburgh, Edinburgh, UK
  • fYear
    2014
  • fDate
    12-17 Oct. 2014
  • Firstpage
    1
  • Lastpage
    10
  • Abstract
    Many of today´s embedded devices are based on MultiProcessor System-on-Chips(MPSoCs) Such devices are usually heterogeneous, containing DSPs and specialized accelerators as well as one or more CPUs. This heterogeneity allows efficient implementations in specialized domains but is a barrier to their wider use. They are difficult to program as only the CPU is directly exposed to the programmer with access to other resources restricted to narrow library interfaces. This paper enables the exploitation of heterogeneous resources from a high level parallel programming model. It presents an LLVM based compiler that maps OpenMP programs to the underlying heterogeneous cores using an SPMD model of computation. It partitions data and computation across the cores, managing synchronization and memory coherence across different memory domains and operating systems. We evaluate its performance on the OMAP4 MPSoC on a range of data parallel benchmarks. On average it gives a 2.75x speedup over using the low-level library approach. Further-more, it gives a speedup of 1.38x and an improved energy efficiency of 1.4x over using the two A9 cores alone.
  • Keywords
    high level languages; multiprocessing systems; parallel programming; program compilers; synchronisation; system-on-chip; A9 cores; LLVM based compiler; OMAP4 MPSoC; Open Multimedia Applications Platform(OMAP); OpenMP programs; SPMD model; Single Program Multiple Data; compiler framework; data parallel benchmarks; data parallel program mapping; energy efficiency; heterogeneous MPSoCs; heterogeneous cores; high level parallel programming model; memory coherence; multiprocessor system-on-chips; operating systems; synchronization; Arrays; Computational modeling; Digital signal processing; Instruction sets; Programming; Synchronization; Compiler, SPMD, data; heterogeneous processors; parallel;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Compilers, Architecture and Synthesis for Embedded Systems (CASES), 2014 International Conference on
  • Conference_Location
    Jaypee Greens
  • Type

    conf

  • DOI
    10.1145/2656106.2656107
  • Filename
    6972462