Title :
Measurement of power supply noise tolerance of self-timed processor
Author :
Asada, Kunihiro ; Sogabe, Taku ; Nakura, Toru ; Ikeda, Makoto
Author_Institution :
Dept. of Electron. Eng., Univ. of Tokyo, Tokyo
Abstract :
We have compared the power supply noise tolerance of a synchronous processor and a self-timed processor fabricated using 0.18mum CMOS. We have designed the self-timed processor using the same RTL as the synchronous processor, and translated it into a netlist with DCVSL circuits and completion logic trees. We have demonstrated the synchronous processor shows an error rate of 9.3% for the worst power supply noise in case of 10% timing margin design. On the other hand, the self-timed processor shows 40% speed degradation, but no error, for the same power supply noise.
Keywords :
CMOS integrated circuits; integrated circuit design; power integrated circuits; CMOS; DCVSL circuits; completion logic trees; error rate; power supply noise tolerance; self-timed processor; synchronous processor; worst power supply noise; CMOS logic circuits; CMOS process; Circuit noise; Error analysis; Logic circuits; Logic design; Noise measurement; Power measurement; Power supplies; Process design;
Conference_Titel :
Design and Diagnostics of Electronic Circuits & Systems, 2009. DDECS '09. 12th International Symposium on
Conference_Location :
Liberec
Print_ISBN :
978-1-4244-3341-4
Electronic_ISBN :
978-1-4244-3340-7
DOI :
10.1109/DDECS.2009.5012112
