DocumentCode :
170695
Title :
Control-layer optimization for flow-based mVLSI microfluidic biochips
Author :
Kai Hu ; Trung Anh Dinh ; Tsung-Yi Ho ; Chakrabarty, Krishnendu
Author_Institution :
Duke Univ., Durham, NH, USA
fYear :
2014
fDate :
12-17 Oct. 2014
Firstpage :
1
Lastpage :
10
Abstract :
Recent advantages in flow-based microfluidic biochips have enabled the emergence of lab-on-a-chip devices for bimolecular recognition and point-of-care disease diagnostics. However, the adoption of flow-based biochips is hampered today by the lack of computer-aided design tools. Manual design procedures not only delay product development but they also inhibit the exploitation of the design complexity that is possible with current fabrication techniques. In this paper, we present the first practical problem formulation for automated control-layer design in flow-based microfluidic VLSI (mVLSI) biochips and propose a systematic approach for solving this problem. Our goal is to find an efficient routing solution for control-layer design with a minimum number of control pins. The pressure-propagation delay, an intrinsic physical phenomenon in mVLSI biochips, is minimized in order to reduce the response time for valves, decrease the pattern set-up time, and synchronize valve actuation. Two fabricated flow-based devices and five synthetic benchmarks are used to evaluate the proposed optimization method. Compared with manual control-layer design and a baseline approach, the proposed approach leads to fewer control pins, better timing behavior, and shorter channel length in the control layer.
Keywords :
VLSI; biological techniques; lab-on-a-chip; microfluidics; microvalves; optimisation; automated control-layer design; bimolecular recognition; channel length; computer-aided design tool; control pin; control-layer optimization; fabrication technique; flow-based microfluidic VLSI biochip; lab-on-a-chip device; manual design procedure; pattern set-up time; point-of-care disease diagnostic; pressure-propagation delay; response time; synthetic benchmark; valve actuation synchronization; very-large-scale integration; Delays; Microchannels; Mixers; Multiplexing; Pins; Routing; Valves;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Compilers, Architecture and Synthesis for Embedded Systems (CASES), 2014 International Conference on
Conference_Location :
Jaypee Greens
Type :
conf
DOI :
10.1145/2656106.2656118
Filename :
6972469
Link To Document :
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