Optimizing temperature distribution in modern processors through efficient floorplanning

In modern integrated circuits, reducing the hotspot temperature even by several degrees may lead to significant advantages. In particular, in high performance processors, lower temperature means lower cooling costs, the possibility of increasing the operating frequency and extending the devices lifetime. Therefore, in this paper we investigate how the positioning of particular processor units in the floorplan (i.e. floorplanning) affects the maximal temperature in the chip. We take into consideration 8- and 6-core processors and simulate the temperature distribution for various floorplan designs. It is shown that the difference in maximal temperature for various floorplans can reach even 7.2K for a typical case. It is also argued that the 6-core design may be a better option for future processors fabricated in 14 nm technology.