A 20nm 112Mb SRAM in High-к metal-gate with assist circuitry for low-leakage and low-VMIN applications

A 20nm high-κ metal-gate planar CMOS technology is optimized and developed for SoC platform applications that span a wide range of power and performance. This technology is based on a 20nm SoC process featuring high-κ metal gate and strain techniques for core logic transistors with low-power/high-performance and I/O transistors. A high-density and a high-performance embedded memory bit cell each has an area <;0.1μm². This technology is targeted to high-density low-cost low-power high-performance applications, such as mobile applications with video. Increased threshold-voltage variation of scaled transistors reduces the static noise margin (SNM) and write margin (WM) of the SRAM bit cell. The effect is more predominant for the high-density SRAMs due to small device sizes and large memory capacity requirement for modern SoC design. Therefore, chip performance and minimum operating voltage (V_DDmin) are both degraded by the embedded SRAM. Reducing the pass-gate strength or BL capacitance with slow WL rise are effective techniques to improve the SRAM cell stability [1,2]. Underdriving the pass-gate reduces the bit-cell read current but also reduces WM, resulting in SRAM performance degradation. Physically shortening the BL limits the SRAM array configuration. Lowering the SRAM cell power supply improves the WM [3,4], but is less effective than the negative-bitline-based write-assist technique. Compared to conventional techniques, this work presents a partially suppressed wordline (PSWL) scheme for read assist and a bitline-length-tracked negative-bitline-boosting (BT-NBL) scheme for write assist without significantly degrading SRAM performance. With the read/write assist circuitry, the overall V_DDmin improvement is over 200mV in a 112Mb SRAM test-chip.