Title :
A 27% active and 85% standby power reduction in dual-power-supply SRAM using BL power calculator and digitally controllable retention circuit
Author :
Tachibana, F. ; Hirabayashi, O. ; Takeyama, Y. ; Shizuno, M. ; Kawasumi, A. ; Kushida, K. ; Suzuki, A. ; Niki, Y. ; Sasaki, Seishi ; Yabe, Tatsuro ; Unekawa, Y.
Author_Institution :
Toshiba, Kawasaki, Japan
Abstract :
This paper presents a dual-power-supply SRAM that reduces active and standby power from room temperature (RT) to high temperature (HT) using a BL power calculator (BLPC) and a digitally controllable retention circuit (DCRC). A test-chip is fabricated in a 28nm CMOS technology with a 0.120μm2 6T-SRAM cell. With these schemes, active and standby power consumptions at 25°C are reduced by 27% and 85%, respectively.
Keywords :
CMOS memory circuits; SRAM chips; BL power calculator; BLPC; CMOS technology; DCRC; HT; RT; active power consumption reduction; digitally-controllable retention circuit; dual-power-supply SRAM cell; high temperature; room temperature; size 28 nm; standby power consumption reduction; temperature 25 degC; test chip; CMOS integrated circuits; Calculators; Logic gates; Power demand; SRAM cells; Temperature control;
Conference_Titel :
Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2013 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4673-4515-6
DOI :
10.1109/ISSCC.2013.6487752
