DocumentCode :
1707806
Title :
A 56.4-to-63.4GHz spurious-free all-digital fractional-N PLL in 65nm CMOS
Author :
Wanghua Wu ; Xuefei Bai ; Staszewski, Robert Bogdan ; Long, John R.
Author_Institution :
Delft Univ. of Technol., Delft, Netherlands
fYear :
2013
Firstpage :
352
Lastpage :
353
Abstract :
Frequency synthesis at mm-Waves is still dominated by analog PLLs, although all-digital PLLs (ADPLLs) [1] have been widely explored below 10GHz. The major obstacle has been the poor quality of digitally controlled oscillators (DCO) as MOS varactor Q-factor drops to <;10 at 60GHz. A mm-Wave digital transmitter (TX) based on a 60GHz fractional-N ADPLL with two-point FM is proposed here. The TX features extensive reconfigurability and permits the highest degree of integration of RF and baseband circuitry for low-cost, high-volume applications. To simplify the TX architecture, the synthesizer is capable of FM, hence a time-to-digital converter (TDC) is preferred over bang-bang phase detection. With the aid of autonomous calibrations of DCO and TDC gain, wideband two-point FM is achieved.
Keywords :
CMOS digital integrated circuits; digital phase locked loops; field effect MIMIC; CMOS; MOS varactor; Q-factor; digitally controlled oscillators; frequency 56.4 GHz to 63.4 GHz; frequency synthesis; size 65 nm; spurious free all digital fractional-N PLL; time-to-digital converter; CMOS integrated circuits; Frequency shift keying; Metals; Phase locked loops; Solid state circuits; Strips;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2013 IEEE International
Conference_Location :
San Francisco, CA
ISSN :
0193-6530
Print_ISBN :
978-1-4673-4515-6
Type :
conf
DOI :
10.1109/ISSCC.2013.6487766
Filename :
6487766
Link To Document :
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