Title :
Settling time design considerations for SC integrators
Author :
Chilakapati, Uma ; Fiez, Terri
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., Washington State Univ., Pullman, WA, USA
Abstract :
Using the return-ratio approach, a model is developed to optimize the switched-capacitor (SC) integrator settling time. This model is used to determine the phase margin of the open-loop amplifier to achieve minimum settling time as a closed-loop SC integrator. The sampling switch resistance affects the integrator settling time while the feedback switch resistance has negligible effect
Keywords :
integrating circuits; switched capacitor networks; closed-loop SC integrator; feedback switch resistance; open-loop amplifier; phase margin; return ratio model; sampling switch resistance; settling time design; Computer science; Design optimization; Equivalent circuits; Feedback; Feedforward systems; Frequency; Operational amplifiers; Sampling methods; Switches; Transfer functions;
Conference_Titel :
Circuits and Systems, 1998. ISCAS '98. Proceedings of the 1998 IEEE International Symposium on
Conference_Location :
Monterey, CA
Print_ISBN :
0-7803-4455-3
DOI :
10.1109/ISCAS.1998.704510
