Noise analysis and optimization of power constrained integrated inductive degradation LNAs

Author

Gong, Fei ; DeGroat, Joanne

Author_Institution

Dept. of Electr. & Comput. Eng., Ohio State Univ., Columbus, OH, USA

fYear

2009

Firstpage

121

Lastpage

125

Abstract

When the matching inductors of low noise amplifiers (LNAs) are moved from off chip to on chip, their noise contribution cannot be neglected. This paper investigates the noise performance of an integrated source inductive degradation LNA, analyzes the noise contribution of its input matching inductors, and proposes a noise optimization method for the input matching network design of a power constrained LNA. The result was verified with a 2GHz LNA design in CMOS 0.18Â¿m technology. When the current is constrained to a maximum of 3mA, the LNA achieves a noise figure of 3dB and an input return loss of -40dB.

Keywords

CMOS analogue integrated circuits; low noise amplifiers; CMOS technology; current 3 mA; frequency 2 GHz; input matching network design; loss -40 dB; low noise amplifiers; noise figure 3 dB; noise optimization method; power constrained integrated inductive degradation LNA; size 0.18 mum; CMOS technology; Constraint optimization; Degradation; Impedance matching; Inductors; Noise figure; Optimization methods; Performance analysis; Receivers; Transducers;

fLanguage

English

Publisher

ieee

Conference_Titel

Aerospace & Electronics Conference (NAECON), Proceedings of the IEEE 2009 National

Conference_Location

Dayton, OH

Print_ISBN

978-1-4244-4494-6

Electronic_ISBN

978-1-4244-4495-3

Type

conf

DOI

10.1109/NAECON.2009.5426642

Filename

5426642