A 3.1mW phase-tunable quadrature-generation method for CEI 28G short-reach CDR in 28nm CMOS

Generating quadrature phases at low area and power overhead from a two-phase clock without frequency conversion is desirable for half-rate CDR architectures. This is useful for both embedded and forwarded clock systems, where quadrature generation by dividers, ring oscillators or coupled LC-VCOs is common. For example, [1] uses LC-VCOs followed by 2:1 dividers to generate the half-rate clocks for both TX and RX in a 28Gb/s transceiver. However, such an approach tends to be power- and area-inefficient for multi-lane implementations at data rates of 25Gb/s and beyond.