Title :
Reliable and energy-efficient 1MHz 0.4V dynamically reconfigurable SoC for ExG applications in 40nm LP CMOS
Author :
Konijnenburg, Mario ; Yeongojn Cho ; Ashouei, M. ; Gemmeke, T. ; Changmoo Kim ; Hulzink, J. ; Stuyt, J. ; Mookyung Jung ; Huisken, J. ; Soojung Ryu ; Jungwook Kim ; de Groot, Harmke
Author_Institution :
imec - Holst Centre, Eindhoven, Netherlands
Abstract :
Wireless Sensor Nodes (WSN) have a wide range of applications in health care and life style monitoring. Their severe energy constraint is often addressed through minimizing the amount of transmitted data by way of energy-efficient on-node signal processing. The rationale for this approach is that a large portion of WSN energy is consumed by the radio communication even for very low-data-rate situations [1]. Efficient on-node processing has been the subject of recent work, with the common element being aggressive voltage scaling into the sub-threshold region [2-4]. A major assumption of the existing works is that the amount of required computation is low, justifying an on-node processor with limited computational capability. While this might be the case for many applications of WSNs, emerging ambulatory biomedical signal processing applications exceed the performance offered by today´s on-node processors.
Keywords :
CMOS digital integrated circuits; DC-DC power convertors; biomedical electronics; circuit optimisation; clocks; energy conservation; energy consumption; failure analysis; integrated circuit noise; leakage currents; medical signal processing; multiprocessing systems; performance evaluation; power aware computing; reconfigurable architectures; system-on-chip; timing; voltage control; wireless sensor networks; ExG applications; LP CMOS technology; WSN energy consumption; aggressive power gating; application-driven dynamic voltage and frequency scaling; automatic power switch bias voltage control; body bias voltage optimization; clock generation circuitry; cooptimisation; data transmission minimization; energy constraint; energy-efficient dynamically reconfigurable SoC; energy-efficient on-node signal processing; fine-grain power gating; frequency 1 MHz to 150 MHz; health care applications; leakage mitigation; life style monitoring; low static noise margin; mobile biomedical signal processing applications; on-chip all-digital DC-DC converters; on-node processor; performance monitoring circuitry; power switches; process variability; radiocommunication; reconfigurable VLIW processor; simulation-based cell library selection; size 40 nm; subthreshold region; supply voltage optimization; timing failure detection; voltage 0.4 V to 1.1 V; wireless sensor nodes; Computer architecture; Energy efficiency; Monitoring; System-on-chip; Timing; Voltage control; Wireless sensor networks;
Conference_Titel :
Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2013 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4673-4515-6
DOI :
10.1109/ISSCC.2013.6487801
