Intermittent resonant clocking enabling power reduction at any clock frequency for 0.37V 980kHz near-threshold logic circuits

In order to improve the energy efficiency of logic circuits, reductions in capacitance (C) and power supply voltage (V_DD) are required, as energy consumption is proportional to CV_DD2. Near-threshold (V_t) operation achieves an energy minimum. Resonant clocking can reduce the effective capacitance of the clock distribution network. In this work, a new resonant clocking scheme enabling power reduction at any clock frequency is proposed and applied to a 0.37V 980kHz near-V_t logic circuit in 40nm CMOS.