DocumentCode :
1708930
Title :
Optimization of via contact test structure for electro-migration
Author :
Yamamoto, Shigehisa ; Komori, Junko ; Takata, Yoshifumi ; Sekine, Masahiro ; Koyama, Hiroshi
Author_Institution :
ULSI Lab., Mitsubishi Electr. Corp., Itami, Japan
fYear :
1997
Firstpage :
67
Lastpage :
71
Abstract :
The effects of via contact test structure on electromigration (EM) lifetime were investigated. We model the median-time-to-failure (MTF) and log-normal dispersion of the failure time (σ) of via contacts with consideration to stress-induced backflow effect and Al drift velocity. The MTF and σ are described as a function of the critical length and the length between vias of via contact test structure and increase as the length between vias approaches the critical length. Also, MTF and σ depend on stress current density in accelerated EM test. We propose an optimized via contact test structure and accelerated conditions for the accurate extrapolation of EM lifetime of multilevel interconnects
Keywords :
VLSI; electromigration; failure analysis; integrated circuit interconnections; integrated circuit metallisation; integrated circuit modelling; integrated circuit reliability; integrated circuit testing; Al; Al drift velocity; MTF; accelerated EM test; accelerated conditions; critical length; electromigration lifetime; failure time; log-normal dispersion; median-time-to-failure; model; multilevel interconnects; stress current density; stress-induced backflow effect; via contact test structure; Circuit testing; Electron mobility; Extrapolation; Integrated circuit interconnections; Life estimation; Life testing; Stress; Tin; Very large scale integration; Virtual colonoscopy;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Microelectronic Test Structures, 1997. ICMTS 1997. Proceedings. IEEE International Conference on
Conference_Location :
Monterey, CA
Print_ISBN :
0-7803-3243-1
Type :
conf
DOI :
10.1109/ICMTS.1997.589338
Filename :
589338
Link To Document :
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