Title :
Area efficient and high throughput CAVLC encoder for 1920×1080@30p H.264/AVC
Author :
Han, Chang Su ; Lee, Jae Hun
Author_Institution :
Digital Media R&D Center, Samsung Electron. Co, Ltd.
Abstract :
This paper proposes a high performance hardware architecture design for the H.264/AVC CAVLC encoder. The proposed architecture can make a realtime process for 1920 times 1080 @ 30p. With the synthesis constraint of a 114 MHz clock, the hardware cost of the proposed design is 7389 gates based on SS65LP 65 nm technology.
Keywords :
video coding; AVC; H.264; area efficient encoder; frequency 114 MHz; hardware architecture design; high throughput CAVLC encoder; Automatic voltage control; Buffer storage; Concatenated codes; Costs; Encoding; Entropy coding; Hardware; Research and development; Throughput; Video coding;
Conference_Titel :
Consumer Electronics, 2009. ICCE '09. Digest of Technical Papers International Conference on
Conference_Location :
Las Vegas, NV
Print_ISBN :
978-1-4244-4701-5
Electronic_ISBN :
978-1-4244-2559-4
DOI :
10.1109/ICCE.2009.5012195
