Title :
A 14b 2.5GS/s 8-way-interleaved pipelined ADC with background calibration and digital dynamic linearity correction
Author :
Setterberg, B. ; Poulton, K. ; Ray, Sambaran ; Huber, D.J. ; Abramzon, V. ; Steinbach, G. ; Keane, J.P. ; Wuppermann, B. ; Clayson, M. ; Martin, Miquel ; Pasha, R. ; Peeters, E. ; Jacobs, A. ; Demarsin, F. ; Al-Adnani, A. ; Brandt, P.
Author_Institution :
Agilent Technol., Santa Clara, CA, USA
Abstract :
Metastable events in ADC comparators cause large errors that cannot be tolerated in test and measurement applications that record data over extended time intervals. This work utilizes BiCMOS technology to provide high dynamic range analog-to-digital conversion at 2.5GS/s with a metastable error rate of less than one error per year and better than 78dB SFDR over a 1GHz BW.
Keywords :
BiCMOS integrated circuits; analogue-digital conversion; calibration; ADC comparator; BiCMOS technology; analog-to-digital conversion; background calibration; digital dynamic linearity correction; frequency 1 GHz; interleaved pipelined ADC; metastable error rate; metastable event; Analog-digital conversion; Calibration; Clocks; Finite impulse response filters; Linearity; Solid state circuits; Transient analysis;
Conference_Titel :
Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2013 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4673-4515-6
DOI :
10.1109/ISSCC.2013.6487817
