Title :
A 3.1mW 8b 1.2GS/s single-channel asynchronous SAR ADC with alternate comparators for enhanced speed in 32nm digital SOI CMOS
Author :
Kull, Lukas ; Toifl, Thomas ; Schmatz, Martin ; Francese, Pier Andrea ; Menolfi, Christian ; Braendli, Matthias ; Kossel, Marcel ; Morf, Thomas ; Andersen, Toke Meyer ; Leblebici, Yusuf
Author_Institution :
IBM Res., Rüschlikon, Switzerland
Abstract :
Next-generation digital high-speed links require fast, yet energy-efficient ADCs at minimum area. Recent years saw impressive progress in SAR ADC designs towards higher sampling speed. Asynchronous clocking, redundant capacitive DACs (CDAC), multi-bit decisions per step and interleaved designs have been presented. We present an asynchronous redundant single-channel ADC achieving 1.2GS/s at 1V supply by using two comparators in alternation to relax comparator reset timing. The ADC achieves 39.3dB SNDR and 34fJ/conversion-step with a core chip area of 0.0015mm2.
Keywords :
CMOS digital integrated circuits; analogue-digital conversion; clocks; comparators (circuits); digital-analogue conversion; silicon-on-insulator; CDAC; Si; alternate comparators; digital SOI CMOS; interleaved designs; multibit decisions per step; next-generation digital high-speed links; power 3.1 mW; redundant capacitive DAC; single-channel asynchronous SAR ADC; size 32 nm; synchronous clocking; voltage 1 V; CMOS integrated circuits; Calibration; Capacitors; Clocks; Noise; Switches; Timing;
Conference_Titel :
Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2013 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4673-4515-6
DOI :
10.1109/ISSCC.2013.6487818
