A 14b 80MS/s SAR ADC with 73.6dB SNDR in 65nm CMOS

Successive-approximation ADCs (SARs) have excelled in two spaces: in very-high-SNR applications where the precision and stability of capacitors are leveraged along with the use of large signal swings and in high-speed, low-resolution applications in which the SAR´s low power and simplicity has enabled high levels of time-interleaving. In between, ADCs with greater than 10 effective bits and sample rates above 20MS/s are typically not based on the SAR architecture. The sequential nature of the SAR algorithm makes it difficult to achieve both high speed and high accuracy, as increasing the resolution requires each bit decision to be both faster and lower noise. This paper presents a SAR that overcomes some of the conventional speed limitations; it uses a 1.2V-only supply and achieves >70dB SNDR at 80MS/s, which extends the state of the art while maintaining comparable FoM.