DocumentCode
1709488
Title
A VLSI architecture of a random pulse neural network
Author
Yeap, T. ; Vukovitch, G. ; Watanabe, K. ; Petriu, E.
Author_Institution
Dept. of Electr. Eng., Ottawa Univ., Ont., Canada
Volume
1
fYear
1995
Firstpage
207
Abstract
The paper presents an architecture of a 1-bit random-pulse neural network suitable for VLSI implementation. The architecture consists of neurons constructed using a simple digital circuit and this provides a high packing density in a VLSI chip. Simulations results show that a reasonable computational accuracy can be achieved using a small bit-stream length
Keywords
VLSI; digital integrated circuits; neural chips; neural net architecture; 1 bit; VLSI architecture; VLSI chip; VLSI implementation; computational accuracy; digital circuit; high packing density; neurons; random pulse neural network; simulations results; small bit-stream length; Analog computers; Circuit simulation; Computer architecture; Digital circuits; Neural networks; Neurons; Shift registers; Stochastic processes; Stochastic resonance; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Electrical and Computer Engineering, 1995. Canadian Conference on
Conference_Location
Montreal, Que.
ISSN
0840-7789
Print_ISBN
0-7803-2766-7
Type
conf
DOI
10.1109/CCECE.1995.528110
Filename
528110
Link To Document