Leakage power consumption in FPGAs: Thermal analysis

Current power saving techniques have been focused on reducing the dynamic power consumption induced by switching activity in CMOS digital circuits. Among these techniques, we can cite the clock gating, dynamic voltage frequency scaling, adaptive voltage scaling, and multiple voltage thresholds. Recently, as transistor sizes get smaller, the leakage power consumption has become a non-negligible and dominating part of the total power consumption. Thus, it is essential to take care of this new constraint in order to design low-power embedded wireless communication systems. It´s well known that there are a strong relationship between leakage power and die-temperature, so that the larger leakage power consumption is associated with the higher temperature. In this paper we give a detailed analysis of FPGA leakage power consumption based on die temperature measurement. Also, after discretizing the FPGA area into several rectangular regions, we investigate whether dynamic partial reconfiguration technique can be performed over different regions to decrease average die-temperature, and consequently the leakage power consumption.