Title :
An on-chip, interconnect capacitance characterization method with sub-femto-farad resolution
Author :
Chen, James C. ; Sylvester, Dennis ; Hu, Chenming ; Aoki, Hitoshi ; Nakagawa, Sam ; Oh, Soo-Young
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
Abstract :
In this paper, a sensitive and simple technique for parasitic interconnect capacitance measurement with 0.01 fF sensitivity is presented. This on-chip technique is based upon an efficient test structure design. No reference capacitor is needed. Only a DC current meter is required for its measurement. We have applied this technique to extract various interconnect geometry capacitances and compared the results to those from 3D simulations
Keywords :
capacitance measurement; integrated circuit interconnections; integrated circuit measurement; integrated circuit testing; 0.01 fF; DC current meter; interconnect capacitance characterization method; interconnect geometry capacitances; onchip characterization method; parasitic capacitance measurement; sub-femto-farad resolution; test structure design; Capacitance measurement; Capacitors; Circuit testing; Current measurement; Frequency; Geometry; Integrated circuit interconnections; Laboratories; MOS devices; MOSFET circuits;
Conference_Titel :
Microelectronic Test Structures, 1997. ICMTS 1997. Proceedings. IEEE International Conference on
Conference_Location :
Monterey, CA
Print_ISBN :
0-7803-3243-1
DOI :
10.1109/ICMTS.1997.589342
