Testability considerations in high-performance avionics processors

Teledyne Systems has actively pursued the development and introduction of a consistent multilevel digital avionic system hardware design for test (DFT) methodology. This methodology is an evolution of standard logic functions, design rules, techniques, and electronic computer aided design (ECAD) tools, which have been successfully employed on two generations of advanced digital avionic computer systems to address testability at three organizational levels: component, module, and online built-in-self-test (BIST). The benefits are reduced manpower requirements, shorter and more predictable development cycles for larger design, higher levels of quality assurance, and improved maintainability of fielded products