Title :
A design for-testability technique for shorts and bridging faults in BiCMOS logic families
Author :
Raahemifar, K. ; Hessabi, S. ; Elmasry, M.I.
Author_Institution :
Dept. of Electr. & Comput. Eng., Waterloo Univ., Ont., Canada
Abstract :
The paper provides the results of a simulation-based fault characterization study of BiCMOS logic families. The author shows that most of the shorts cause IDDQ faults, while open defects result in delay or stuck-open faults. The author proposes a design-for-testability technique for detecting short and bridging faults in CMOS/BiCMOS logic circuits. The impact of this circuit modification on the behavior of the circuit in normal mode is investigated
Keywords :
BiCMOS digital integrated circuits; BiCMOS logic circuits; design for testability; fault currents; fault diagnosis; integrated circuit design; integrated circuit testing; logic design; logic testing; BiCMOS logic circuits; BiCMOS logic families; CMOS logic circuits; IDDQ faults; bridging faults; circuit modification; delay faults; design for-testability technique; normal mode; open defects; shorts; simulation-based fault characterization; stuck-open faults; BiCMOS integrated circuits; CMOS logic circuits; Circuit faults; Circuit simulation; Circuit testing; Electrical fault detection; Fault detection; Logic circuits; Logic design; MOSFETs;
Conference_Titel :
Electrical and Computer Engineering, 1995. Canadian Conference on
Conference_Location :
Montreal, Que.
Print_ISBN :
0-7803-2766-7
DOI :
10.1109/CCECE.1995.528114
