Sampling jitter in high-speed SI circuits

Random and signal dependent sampling time uncertainty in high-speed switched-current circuits are analyzed, and comparison with voltage-mode sampling is made. The similarity of the two techniques is shown as well as the fact that the lower voltage swing in switched-current circuits, makes them less sensitive to the signal dependent switch-off time of the sampling switch. Derivations and simulation results showing the effects of clock phase-noise, additive clock driver noise, and signal-dependent sampling time uncertainty are included. Reduction of signal-dependent jitter errors by using fully-differential switched-current sampling is also illustrated