DocumentCode :
1712266
Title :
The design of a lumped element impedance-matching network with reduced parasitic effects obtained from numerical modeling
Author :
Jun Fan ; Knighten, James L ; Smith, N.W.
Volume :
3
fYear :
2004
Firstpage :
984
Abstract :
This paper presents an impedance-matching network design with numerical modeling of the parasitic effects. A modeling tool CEMPIE (Circuit Extraction approach based on a Mixed Potential Integral Equation formulation) is used to model the board-level parasitics of surface mount technology (SMT) resistors for impedance-matching networks. A 3-layer design of impedance-matching network with 0402 SMT resistors is implemented according to the modeling results. And its performance is demonstrated.
Keywords :
electromagnetic compatibility; impedance matching; integral equations; lumped parameter networks; printed circuit design; resistors; surface mount technology; 0402 SMT resistors; 3-layer design; CEMPIE modeling tool; Circuit Extraction approach based on a Mixed Potential Integral Equation formulation; board-level parasitics; impedance-matching network; lumped element; numerical modeling; reduced parasitic effects; surface mount technology; Circuit simulation; Electric potential; Impedance matching; Integral equations; Numerical models; Resistors; Surface impedance; Surface-mount technology; Symmetric matrices; Transmission line matrix methods;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electromagnetic Compatibility, 2004. EMC 2004. 2004 InternationalSymposium on
Print_ISBN :
0-7803-8443-1
Type :
conf
DOI :
10.1109/ISEMC.2004.1349960
Filename :
1349960
Link To Document :
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