Instruction set extension for high throughput disparity estimation in stereo image processing

This paper presents the implementation and evaluation of an application-specific instruction set for a customizable RISC-processor for very high throughput stereo image processing. Compared to the base processor the overall processing time is accelerated by a factor of over 130, while the processor silicon area requirement increases only by a factor of 2.9. The processor has been enhanced with algorithm-specific extensions (i.e. special functional units), as well as with extensions that are not restricted to a specific algorithm (e.g. single-instruction-multiple-data). Hereby, the special functional units account for 50% of the speed-up, but less than 14% of the processor silicon area requirement. The proposed processor extensions thereby sustain the full flexibility of a programmable processor while enabling disparity estimation of 640×480 stereo video sequences at 20 fps when running at a clock frequency of 373 MHz.