Title :
An FPGA architecture for solving the Table Maker´s Dilemma
Author :
de Dinechin, Florent ; Muller, J.-M. ; Pasca, B. ; Plesco, A.
Author_Institution :
Lab. LIP, UCBL, Lyon, France
Abstract :
Solving the Table Maker´s Dilemma, for a given function and a given target floating-point format, requires testing the value of the function, with high precision, at a very large number of consecutive values. We give an algorithm that allows for performing such computations on a very regular architecture, and present an FPGA implementation of that algorithm.
Keywords :
field programmable gate arrays; floating point arithmetic; FPGA architecture; floating point format; table maker dilemma; Accuracy; Adders; Approximation methods; Computer architecture; Field programmable gate arrays; Polynomials; Radiation detectors; FPGA; correct rounding; elementary functions; floating-point arithmetic; table maker´s dilemma;
Conference_Titel :
Application-Specific Systems, Architectures and Processors (ASAP), 2011 IEEE International Conference on
Conference_Location :
Santa Monica, CA
Print_ISBN :
978-1-4577-1291-3
Electronic_ISBN :
2160-0511
DOI :
10.1109/ASAP.2011.6043267
